This invention relates to computer interconnect systems, and more particularly to a packet communication system employing dual serial data paths between computer nodes.
In U.S. Pat. Nos. 4,777,595, 4,560,985, 4,490,785, and in copending application Ser. No. 109,503, now U.S. Pat. No. 4,845,722 110,009, now U.S. Pat. No. 4,897,833 and 110,513, now U.S. Pat. No. 4,887,076 filed Oct. 16, 1987, all assigned to Digital Equipment Corporation, assignee of this invention, computer interconnect systems are shown of the type employing packet data transfer using serial paths. These types of computer interconnect systems have been commercially used for processors and bulk memory facilities of the VAX architecture, and provide versatile systems of high performance and reliability. However, with increasing demands for additional functions, compatibility with a wide variety of computer equipment, higher speed, lower cost, larger networks and higher reliability (both of data and hardware), further development of this type of interconnect system is imperative.
The likelihood of completing a packet transfer initiated by a given node in a network of this type is dependent upon whether a serial data channel is free, i.e., not being used for another transfer, and upon whether the destination node itself is free and ready to receive the packet. This likelihood can be increased by having more than one serial data channel interconnecting the nodes. Also, having more than one serial data channel makes possible the simultaneous reception and/or transmission on more than one channel at the same time. While some prior packet communications systems of the type mentioned above have included two transmission channels for each node, these have been for the purpose of redundancy rather than simultaneous use, and so the net maximum data rates are not improved, even though the reliability is enhanced.
Simultaneous data transmission and/or reception has been provided over serial data links by merely replicating all of the port hardware associated with a serial port or communications adapter. This is not only more expensive, occupies more space and consumes more power, but also the ports must be separately addressed by the host computer. That is, it is preferable that the multiple simultaneous paths be transparent to the host computer.
When a packet data stream is being transmitted or received by a node in a system of this type, the data handling circuitry used by the node to deliver the data stream to the transmitter, or accept the incoming data stream from the receiver, must be able to execute the transfer with stalls or delays due to a bus request not being granted, or the like. Any stall during reception or transmission means the packet must be discarded and resent. Since it is not known when packets are going to be received at a node, a received packet must be quickly moved from the receiver to the host computer since another packet may be following immediately.
When a mode in one of the computer interconnect systems mentioned above has a packet to send, the channel connected to this node is checked to see if a carrier is present, and, if not, the packet is sent, without regard for whether or not a channel is free all the way to the destination node, or whether or not the destination node is ready to receive. If the channel is not free or the destination is busy, the packet is discarded. In prior systems of this type, the source node continues to transmit the packet under this condition, even though the packet is being discarded instead of being sent on to the destination node. The packet is then resent after a time since an acknowledge is not received at the source node. If the packet is lengthy, the transmit time wasted by this needless transmission of a packet that is being discarded can adversely affect the system performance.
It is a principal object of this invention to provide an improved computer interconnect system, particularly one which allows increased performance by more efficient use of serial paths between nodes. Another object is to provide an improved high-speed computer interconnect system in which a greater probability of gaining use of a transmission path from one node to another is achieved, yet the component parts of the system are not needlessly duplicated or complex. A further object is to provide a packet data communication system allowing more efficient transmission and/or reception by serial paths between nodes, in which use of the serial paths is maximized by aborting transmission of packets which are not reaching a destination node. An additional object is to provide a packet data transmission and reception system with improved handling at high-performance of dual simultaneous serial channels.